1. Field of the Invention
The present invention relates to copper (Cu) and/or copper alloy metallization in semiconductor devices with improved planarity and reduced defects. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnect structures with improved reliability.
2. Background of the Related Art
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnect technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance and capacitance) interconnect pattern, particularly in applications where submicron vias, contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed dielectric interlayers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines. Typically, the conductive patterns on different layers, i.e,. are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor “chips” comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing an dielectric layer on a conductive layer comprising at least one conductive pattern, forming an opening through the dielectric layer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric interlayer is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section. The entire opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Copper (Cu) and copper alloys have received considerable attention as candidates for replacing aluminum (Al) in interconnect metallization. Copper and copper alloys are relatively inexpensive, easy to process, and have a lower resistivity than aluminum. In addition, copper and copper alloys have improved electrical properties, vis-à-vis tungsten (W), making copper and copper alloys desirable metals for use as a conductive plug as well as conductive wiring.
An approach to forming copper and copper alloy plugs and wiring comprises the use of damascene structures. However, due to copper diffusion through dielectric layer materials, such as silicon dioxide, a diffusion barrier layer for copper interconnect structures is provided between copper or copper alloy interconnect structures and surrounding dielectric materials. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), titanium-titanium nitride (Ti—TiN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for copper and copper alloys. The use of such barrier materials to encapsulate copper is not limited to the interface between copper and the dielectric interlayer, but includes interfaces with other metals as well.
In conventional CMP techniques, a wafer carrier assembly is rotated in contact with a polishing pad in a CMP apparatus. The polishing pad is mounted on a rotating turntable or platen, or moving above a stationary polishing table, driven by an external driving force. The wafers are typically mounted on a carrier which provides a controllable pressure urging the wafers against the polishing pad. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of each thin semiconductor wafer and the polishing pad while dispersing a polishing chemical with or without abrasive particles in a reactive solution to effect both chemical activity and mechanical activity while applying a force between the wafer and a polishing pad.
It is extremely difficult to planarize a copper or copper alloy surface, as by CMP of a damascene inlay, without generating a high degree of surface defects, such as corrosion, scratches, pitting and embedded abrasive particles. A dense array of copper or copper alloy features is typically formed in a dielectric layer, such as a silicon oxide layer, by a damascene technique wherein trenches are initially formed. A barrier layer, such as a tantalum-containing layer, e.g., tantalum (Ta), or tantalum nitride (TaN), is then conformally deposited on the exposed surfaces of the trenches and on the upper surface of the dielectric layer. Copper or a copper alloy is then deposited, as by electroplating, electroless plating, physical vapor deposition (PVD) or chemical vapor deposition (CVD) on the barrier layer, typically at a thickness between about 8,000 Å and about 18,000 Å.
CMP is then conducted to remove the copper or copper alloy overburden stopping on the barrier layer followed by barrier layer removal, employing a mixture of a chemical agent and abrasive particles, to remove the barrier layer, or conducting CMP directly down to the dielectric layer. Copper or copper alloy overburden is material deposited on the substrate in excess of the required amount to fill features formed on the substrate surface. Buffing is optionally conducted on the dielectric layer surface to remove defects, such as scratches in the dielectric materials and further planarize the dielectric material, leaving a copper or the copper alloy filling the damascene opening. The resulting copper or copper alloy filling the dual damascene has an exposed upper surface typically having a high concentration of surface defects. These defects include corrosion, e.g., corrosion stains, microscratches, micropitting and surface abrasive particles. Copper and copper alloy wafers exhibit a much greater tendency to scratch during planarization than dielectric materials, such as oxides or nitrides. Copper and copper alloy surfaces corrode very easily and are difficult to passivate in low pH aqueous environments. Conventional wafer cleaning alone cannot completely eliminate such defects. Conventional practices for planarizing copper or copper alloys disadvantageously result in a high defect count subsequent to planarization. Such surface defects adversely impact device performance and reliability, particularly as device geometries shrink into the deep sub-micron range. Therefore, there exists a need for methodology enabling the planarization of copper and copper alloys with a reduced amount of surface defects. There exists a further need for such enabling methodology that is compatible with conventional polishing techniques and apparatus.